I've gotta say, as AMD moves along, Hector is beginning to sound like Intel did a few years ago. In denial that they had messed up and spinning his story like everyone else has the IQ of a pea:
http://www.crn.com/sections/breakingnews/dailyarchives.jhtml?articleId=197007770
Here are some of the good bits:
"The one thing that's hard to do is trying to correlate the stock price to anything a company does. It is very difficult. We're disappointed that our stock isn't performing better, but I won't correlate it to anything other than it's just one of those things."
Ha ha - the slumping stock price is not related in any way to what's happening in the marketplace. Though I'm sure when the stock was 40 he was saying the market recognises the value of AMD.
CRN: You mentioned the importance of Barcelona. What will be its impact on AMD this year?
RUIZ: This is an incredibly important product transition. We don't expect the ramp [this year] to be dramatic because it's a new core, new micro architecture and platform. The biggest impact it will have is that we'll see a large number of customers and partners align themselves behind the technology.
So at last he admits Barcelona will have no impact on their financials this year.
CRN: When will Barcelona ship?
RICHARD: It's slated for introduction at the end of the second quarter and will be in the market in the third quarter.
Q3 folks...Q3! Around the same time Penryn launches.
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I'm amazed there are no real benchmarks of Barcelona yet. If it will be in the market in Q3, the wafer production would need to start around ~ Apr/May (and therefore masksets and any revisions done by then). As this is only a month or 2 away, why no benchmarks? Are they still rev'ing the masks to address issues?
One would think with the performance simulations they've been touting (40-70%), that they would be eager to back it up with ACTUAL data. If I had to speculate I would guess the LARGE majority of that 40% improvement will be on the power and AMD may be liberal by counting the whole system and using FBDIMMS vs DDR2
As for Ruiz, if I were a shareholder (especially an institutional one) , I would be incredibly pissed off about his statements and AMDs shenanigans in Q4 handling the earnings warnings. this will really start to hurt them when they will need to raise cash, whether it be more stock dilution or loans.
As for Barcelona - this is not surprising at all. The only appreciable volume will be on server (much like Intel's ramp with Core 2), why would folks expect a product which covers <33% of AMD's shipments and will likely be <50% of that 33% expect a huge swing in earnings/revenue. Especially when unit cost will go up due to increased die size and likely lower yield. I doubt (initially) the price will increase by as much as the cost will. Q3 availability is not surprising given AMD's past statements of "mid2007" and given AMD's proclivity for parsing words (65nm will "ship" by end of Q4'06, FX will be "available" in Dec...) - I'm just surprised yahoos like Sharikou were expecting Apr!
K10 will handily beat Penryn
AMD's Kung Fu beats Intel's Voo Doo
"Anonymous said...
K10 will handily beat Penryn
AMD's Kung Fu beats Intel's Voo Doo"
Care to supply a valid benchmark to prove your point? Oppss!!! Thats right, as usual you cant even find a ES of K10. Neither can you find any independent benchmarks. So all your AMD fanbois are FUDDING as usual :P
Btw: Stop hidding behind Anonymous sign. Are you afraid of something?
RUIZ: In spite of all the hype and hoopla, there is not really such thing that Intel has leapfrogged AMD. It's quite the contrary. As a matter of fact, despite all the perceptions of Intel closing the gap, half the time they do a little bit better and the other half we do. And all of that will end with the introduction of Barcelona because it's such a significant jump in performance and quality. I'm confident we will lead in that respect.
Funny how he contradicts himself. In the first part of the paragraph he talks as if Intel is never in the lead and try to close the gap. And then in his last sentence he says Barcelona will help take the lead.
Notice also how in the beginning of the interview he said: ... my point of view, it's four cores in a single piece of silicon and architected with new cores and micro architecture. It will bring a significant new level of performance per watt, and we believe the value to this segment will be really powerful.
performance-per-watt, performance and quality??? Thats it? No quantifiers? better by how much? better than whom? Competition or own self? Hector really sounds too cautious to me compared back when they were beating Intel's offering. It really sounds like they have nothing to show for. Bit scary for AMD.
Of course they will both be in Q3. Intel needs to release something to compete with Barcelona.
This blogger says he just wants to have a discussion, but it's obvious he is biased.
I'm not sure what's going to happen in a few months, but I would bet that AMD's new generation K8L architecture will probably win in a performance battle versus Intel's same Core2 based architecture with a huge 6mb cache. Intel doesn't want to try to fix the FSB bottleneck so they continue to put bandaids on the problem by increasing the cache. The problem with that is that it can only take you so far and this year may just well be the year where the cache bandaid fails to work.
Everything, and I mean Everything, is riding on the K10 (K8L) benchmarks. If they come out as AMD claims with a 40% improvement, then It will mark the end of Intel's short lived speed crown, easily for years to come. But if K10 flops and does not impress, then Intel's new found lead will be measured in years, not months.
Hector was just interviewed saying that he has had customers already using the product. They're simply not releasing any for benchmarking, as is AMD's usual policy.
Intel's 20% claims were backed by erroneous and excessively specific data. Would that be better?
AMD said performance, not ppw, meaning the wattage has nothing to do with their current 40-70% advantage statements.
Why would you be angry as a shareholder? If you own a part of that company and you don't like what it's doing, sell the stock and get over it, don't just whine about it. Seeing as these statements haven't made anyone sell, however, I'd be guessing you'd be in the minority of their shareholders.
AMD said they were only releasing the server in q2, and that it would hit market in appreciable volume in q3. Desktop would be in q3, and would hit appreciable volume in q4. So basically, you're agreeing with him, and are pissed off about it. May I ask why?
"...versus Intel's same Core2 based architecture with a huge 6mb cache. Intel doesn't want to try to fix the FSB bottleneck so they continue to put bandaids on the problem by increasing the cache."
An interesting statement. I wonder how much cache will be on Barcelona? Oh that's right it WILL HAVE 6MB CACHE (L2+L3)...so I guess by your awesome technical analysis, AMD's newest chip coming out will be "bandaided"? Perhaps AMD is using cache to fix the IMC bottleneck? Great analysis, please keep them coming.
"Why would you be angry as a shareholder? If you own a part of that company and you don't like what it's doing, sell the stock and get over it, don't just whine about it"
Well when the top management has a meeting specifically to talk to analysts and neglects to mention a SERIOUS shortfall in earnings and gross margin only to come out 1 month later and try to protect stock price from crashing prior to the q4 earnings release this is playing games (some may say manipulation) with the stock price in order to secure loans at a good int rate.
So why does this matter? Well for one the price would have crashed earlier had AMD warned when they were aware of the issue - this would have allowed stakeholders to sell 2 months earlier and invest in a market where every stock other than AMD's seems to be going up....(that's an intentional exaggeration). I guess you're unfamiliar with the concepts of NPV and opportunity cost?
"AMD said they were only releasing the server in q2, and that it would hit market in appreciable volume in q3."
It must be difficult reading with those AMD rose colored Here is what Ruiz ACTUALLY SAID: "It's slated for introduction at the end of the second quarter and will be in the market in the third quarter.'
Slated for introduction could mean anything especially when in the same sentence he says "in the market in 3rd quarter" - that sort of implies it will NOT be in the market in the 2nd quarter. This means paper launch/start shipping at end of Q2. I guess this is AMD's newest definition of "release" - you know like the Dec'06 65m "release", the Quad Fx "release" at end of year.
Also could you point me to where Hector or ANYONE AT AMD says there will be "appreciable volume" in Q3? (Didn't think so...)
"AMD said performance, not ppw, meaning the wattage has nothing to do with their current 40-70% advantage statements."
Actually they had previously said ppw, and if you look on page 1 of the interview Hector says "It will bring a significant new level of performance per watt"
40-70% performance could mean anything depending on how the #'s come out - it could mean clock for clock, it could mean top Intel model vs top AMD model. It could mean comparison between same TDP's. It could mean ppw. It could mean the entire system factoring in FBDIMMS and chipsets. It could factor in price. As AMD is now focused on "platformance" I suspect it will NOT be sheer chip performance.
I suspect once the benchmarks are out, AMD will create the definition of 40%-70% performance at that point and tell the analysts that they were right...as Ruiz himself states...we are "in the speculation stage"
@m0rk
I made the Kung Fu/Voo Doo remark.
What does Penryn offer thats different, apart from being 45nm?
Intel is using Voo Doo, just tweaking older tech. I really don't know why they cling to the ancient FSB and so slow with monolithic/native quad core.
They are just digging their own grave.
All they can do is rush Penryn out the door because they are righty fearing the day Barcelona hits.
http://www.hexus.tv/show.php?show=28
That's an Interview with Patrick Patla, Director of AMD's Server Workstation Division
He states, in answer to barcelona's performance vs current Opteron performance in single threaded applications...
"depending on the application, anywhere up to 80% faster"
Probably meaning FPU apps specifically will be that high.
also see http://www.hexus.tv/show.php?show=45
that's an interview with AMD's John Fruehe, who builds AMD's channel business for Opteron.
he elaborates more on barcelona's enhancements.. L3 shared cache, 128 floating point, scaling, HT, better memory controller performance, risks of getting into DDR3 too early (too expensive) and talks a bit about cpu+gpu.
Intel boys rightly should enjoy these days while they can.
This is the calm before the storm.
Just wait and see.
K9 will be to p8 as k8 was to p7 it will cream it so bad that it wont be even funny.
K9 is the barcilona core.
40 precent faster than an core 2 would be > 60 precent than k8.
Intel connot make a true "Quad-core" part out of the paper at that time, perhaps? Q2 is for 45nm Quad-cores! Yeah right, yeah right, Intel leads the race whatever the others implemented into their chips.
And benchmarks? No as usual, then why Intel is releasing Conroe's benchmarks even it's in the labs/not selling? Simple, creating buzz, okay now, it's just not fair to compare an ES (Engineering Sample) with an actual on-sale product, so the outcome was 5-10% lead over the competitor rather than the 20% delta it said in the "lab" reports.
AMD is not going to tell us what the numbers are as the person above mentioned, and you were pissed off for the reason that Intel did the same for creating buzz that Conroe "beats" K8 by 20%? What's the matter with all of ya?
You were pissed off just because another company didn't use the same technique to create buzz? What a shame of you!
When intel let loose those benchmarks so early, you know what happened.
everybody stopped buying P4s and intel's market share slid faster than ever before.
they did AMD a favour, as AMD just gobbled up all that market share.
maybe intel figured they were big enough to absorb this loss of share. or maybe they were too dumb to see it coming.
But AMD can't afford to make that mistake.
If they release mind blowing benchmarks too far in advance, their current sales will dramatically fall, as many people will obviously just wait for the K10s to come out.
Intel used Pentium D as a club in retail to beat X2 3800/4200 on the low end, while maintaining adequate prices on C2D. Why couldn't AMD do the same thing using K8 to whip up on C2D?
Oh, I know why. Because there will be a very small window where AMD *might* have dominance between Conroe and Penryn. It's been demonstrated that all the clocks on current C2D are RIDICULOUSLY conservative. If Barcelona is even close, all Intel has to do to maintain perf and perf/watt is bump clock speeds. With 45 nm you'll add a ridiculous amount of headroom to an already ridiculous amount of headroom.
5 GHz Penryns @ 65 Watts anyone wanna bet?
My take is Intel will prioritize it's Server business above everything else and do whatever they can to ensure Barcelona is not beating them hands down there. First, this is the place they make a lot of money and second by successfully doing this they deny AMD ASP growth and hence the ability to fund other parts of the business with server profits.
But I continue to believe things are not going as well with Barcelona as AMD is saying publicly or else we would have seen some kind of convincing demos and data by now considering the product is "slated for introduction at the end of the second quarter".
Random conjecture on why no Barcelona benches:
Suppose for a second Barcelona is better but not overwhelmingly better than Core 2 (say 10%-15).
If they release this info now, new customers are left debating between buying Intel now or waiting ~6-9 months for something marginally better. (I'm talking 1P or 2P systems)
If they wait on releasing the benches and continue to make vague statements on 40% better, than perhaps they hope customers will hold off on a purchase. If the benches only come out ~1-2 months prior to availability, it may be worth waiting an extra month or two to buy Barcelona even for a small performance advantage.
The other option is they are still doing steppings trying to address either power or speed issues.
Last thought - perhaps they believe Barcelona will only cannibalize their own K8 sales and therefore it is not worth publishing benches now (might as well try to sell as many more k8 servers as they can between now and Q3). Based on where AMD's margins/earnings were for Q4'06, if Barcelona cannibalizes any of their server business the Q1, Q2, Q3 will be very bloody.
I find it hard to believe Ruiz would continue with the Barcelona 40% statements if there was something SERIOUSLY wrong (whether or not it ends up 40% can be spun by AMD PR people). But given the Q1 earnings screwup/mishandling of announcements I doubt AMD would be willing to attempt this again.
My guess is ~15% better performance based on performance per watt metric. With Intel 45nm this lead will evaporate due to power reductions REGARDLESS of any potential clock frequency benefits from high K due to Vt (and thus Vcc)reductions. If high K performance is as advertised AMD will be back in a MHz (GHZ) race and having to rush 45nm to production.
"It's been demonstrated that all the clocks on current C2D are RIDICULOUSLY conservative."
and even better still:
"5 GHz Penryns @ 65 Watts anyone wanna bet?"
Sounds like Netbust all over again. Must be scared that the IPC lead isn't going to stand up to the coming onslaught. Don't be scurred. The fact that a chip can OC doesn't mean it can be guaranteed to run at that speed without errata. Also, in the spirit of the conservation of energy, you can't OC a chip without inceasing the amount of energy it consumes. For example, a 65 watt Allendale E4300 OC'ed to 3.0Ghz will consume about double its speced wattage. And an X6800 OC'ed to what 5.0Ghz will conservatively consume 175 watts. What were you saying about perf/watt? Quite surprisingly, Intel isn't as silly as its fanbois and have clocked C2D right where it should be for its stated thermal envelope. Even with a 45nm process you won't see 4Ghz. If they couldn't hit 4Ghz with a 31 stage pipeline, how do you think they're gonna hit it with a 14 stage even given process improvements. Nope, 3.4-3.6Ghz is all you get from Penryn.
On desktops Core 2 is easily ~20 faster per mhz than K8. That's why 1.86Ghz Core 2 E6300 can compete with a 2.4Ghz Athlon X2. On servers Intel's quad core is incredibly popular and beats AMD in all the benchmarks.
AMD's only hope is Barcelona. Penryn is scheduled for Q3'07. Just in time to greet AMD. Barcelona will only come with 2.3Ghz clockspeed at launch.
We don't know how high Penryn will clock yet, so there's no point in wildly speculating. But we do know Pat Gelsinger announced they are going to do a 3Ghz/1600 FSB Clovertown. It's reasonable to assume that Penryn will be clocked higher than 3Ghz for both dual and quad core.
With this high clockspeed advantage Bareclona will have to be a lot faster per mhz than Penryn.
We know that Penryn dual cores will have 6mb cache, quad core 12mb cache. This is a 50% increase over current parts. There is also SSE4 in there. I predict, on average, that will amount to an improvement of ~5% per mhz. Maybe a little more (10%?) in applications that use SSE heavily.
OK, maybe 5 GHz is optimistic, but:
85 Watts at 2.9 GHz is X6800 envelope on initial spins of silicon that were released 8 months ago. They will bag 10-20 watts with better steppings, so let's say 3.2 GHz JUST with continuous improvement on the 65 nm node. I think this is still conservative. There were also rumors of a 3.2 GHz conroe on a 1333 bus. Still entirely possible.
Second, even a "DUMB" shrink will get them 400 Mhz. PDP800 to PDP900 got them 3.2 to 3.6 GHZ, respectively....so add another 400 MHz....we are up to 3.6 Ghz.
Third, Intel will use a new material at 45 mn that will be much lower-leakage (5x is the claim) than the material at 65 nm. Could they ONLY get 400 MHz additional out of the new material to get to 4 GHz? What if it's 1 GHz? It's possible with 5x less leakage.....
Then you are within spitting distance of 5 GHz. I think it is entirely possible. But some of them fanbois who overclock might have a "daily driver" that is rock stable at 5 GHz. Maybe not at 65 watts, but definitely less than 100. PDP envelope was 130W as a comparison.
The new silicon material is what Intel needed 2 years ago to release Tejas, the 5-6 GHz Netburst. But it was not ready then. Now it is.
And I wear the Intel fanboy badge with honor, thank you very much. Feel free to rip this to shreds, you won't hurt my feelings.
First Barcelona 3's (still a bit vague)
http://www.eetimes.com/news/semi/showArticle.jhtml;jsessionid=MLCHI3FDGGQXMQSNDLRCKHSCJUNN2JVN?articleID=197700269
42% FP doesn't actually sound all that impressive especially as it is compared to today's best Intel processor (might there be a slightly better one come out in 6 months?)
I wonder what the Int performance will be?
anonymous
It's been demonstrated that all the clocks on current C2D are RIDICULOUSLY conservative.
Where was this demonstrated? Do you have a link?
With 45 nm you'll add a ridiculous amount of headroom to an already ridiculous amount of headroom.
The indications are that Intel currently has no headroom on 65nm.
5 GHz Penryns @ 65 Watts anyone wanna bet?
I'll put up $5,000 that Intel will not release any 5.0Ghz Penryns in 2008. How do we make this official?
I'm sure you won't be taking that bet. The truth is that it is nonsense to believe that Penryn will even be released at 4.0Ghz in 2008. Even on Forumz the discussion was only 3.6Ghz.
anonymous, decreasing leakage does not immediately decrease power usage by an immense factor. In fact, leakage only creates a very small portion of power usage and heat generation. Any voltage running through a lower resistance system will have high power usage, it's science. V=IR and all that good stuff.
Also, penryn is just a dumb shrink. Ya, it has more cache, but cache very closely follows the law of diminishing returns.
Also, to whoever said Barcelona will have 6 megs is smoking some pretty strong stuff. 512kb per core, and 2Mb for l3. If you really want to get into it, they also have 512kb in total l1 cache.
On desktop apps, conroe is sometimes 20 or almost 20. Chances are that for the average user, it's worse because of cheap ram, but conroe can deal with bad latency. Barcelona will have the same ability, plus low latency, plus much better branch predicting. Early estimates that are "conservative" are 40% better on desktop apps than k8 was. Also, remember that AMD hasn't changed the fact that there will be a 2.9 ghz desktop release point in q3. They've only changed server yet, though I assume there will be a decrease in desktop speed as well.
Also, k8 will have sse4 as well, just in case whoever brought that up missed it. They'll also have a double width bus for sse instructions, and they are also making other microinstructions into things that are essential like sse. They'll also be able to use their FP unit for sse now (anandtech even says so) so I'm guessing that means even more sse performance enhancement (unless they technically already do, as I may not know what I'm talking about).
I wont rip you for being a fan boy, I probably have my own faults and missteps as someone who dislikes Intel.
"Also, penryn is just a dumb shrink."
This actually isn't entirely true, besides the cache size their are some minor architectural changes. If you actually worked in the industry, you would understand you are mis-using the terminology "dumb shrink".
"anonymous, decreasing leakage does not immediately decrease power usage by an immense factor. In fact, leakage only creates a very small portion of power usage and heat generation."
While I was not the anonymous poster on this, you again are showing your lack of knowledge. There are NUMEROUS types of leakage types on transistors which affects both ACTIVE and IDLE power consumption. Some modeling by NC State suggests that offstate power consumption will account for ~50% of overall power chip consumption (I assume this modeling was done using SiO2 as the gate dielectric, but I do not know for sure). I would consider 50% to be a significant factor.
While fmax (idsat) and Vcc will still drive the power consumption, the ability to improve leakage allows for the advent of lower Vt (transistor threshold voltage) whic hin turn allow your supply voltages to be lowered. This is why you see supply voltages go down with newer technology nodes.
The "leakiest" transistors in a chip are the low Vt ones which is why both Intel and IBM use a dual (and I think IBM may now use a triple) Vt design. For speed critical paths they use low Vt devices and sacrifice leakage (and power consumption) for performance while for non-critcal paths they use higher Vt devices which helps power consumption.
The ability to control leakage SUBSTANTIALLY affects the ability to lower Vt and hence your input voltage. I'll get off my soapbox now - let me know if you have any (intelligent) questions.
"I'll put up $5,000 that Intel will not release any 5.0Ghz Penryns in 2008"
While I was not the anonymous idiot who made the 5.0 Ghz claim your response is just as stupid - why would Intel NEED to release a 5Ghz Penryn, even if they had the capability (which I too, doubt they would have in 2008).
Hey I'll bet you the sun rises tomorrow! Than you captain obvious!
Next thing you know you'll be spewing more of your babble on how the Intel's and AMD's 65nm processes cost the same with no actual factual backing.
...and ignore the cost differences between
1) using 9 metal layers vs 10 layers (I mean heck this only add an extra ILD deposition, etch stop deposition, 2 oxide etch steps, barrier seed, Cu plate,Cu CMP, and 2 lithography steps), and of course doesn't introduce any potential yield hits with all of that additional processing.
2) SSOI vs Si yes let's use some marketing fluff from an SOI supplier (who obviously has no business interest in say makin SOI to be as cheap as possible?!?!) to say it's only SOI is only a 5% cost adder when in reality the substrates adds 10-15% to overall wafer cost.
3) Ignore several other extra processing steps IBM uses for 65nm technology (third Vt step which adds 2 implant and 2 litho steps), additional strain steps...
And I won't even go into 45nm when IBM's "advenced" capabilities uses immersion litho - I mean this only takes the litho tool cost from $20Mil/tool (dry 193nm) to $40Mil/tool (immersion 193nm). It's unfortunate that Intel is behind and is able to use tools that are 1/2 as cheap to accomplish the same feature size. I mean why extend proven technology when you can use newer, more expensive, and more complicated equipment to accomplish the same thing?
"On desktop apps, conroe is sometimes 20 or almost 20. Chances are that for the average user, it's worse because of cheap ram, but conroe can deal with bad latency"
This is a rather curious comment - I assume the 20 refers to 20% better than K8? You then go on to say it might be less because the average user is likely using cheap ram.
Out of curiosity is K8 more or less sensitive to "cheap ram" than the Core 2 architecture? If you compared Core2 to K8 with cheaper RAM would the delta in performance be greater or smaller?
"The indications are that Intel currently has no headroom on 65nm."
"The indications" - is this based on your previously demonstrated expertise in process technology?
Keep in mind "headroom" could also mean lower power parts - rather than jack up fmax, you could use leakage/other transistor improvements within a technology node to lower power. You could also choose not to take advantage of potential headroom to maximize yields and/or binsplits or drive down costs or maximize capacity.
Unless you actually work for Intel's process development team you have no way of knowing what headroom there is on 65nm. Perhaps you can educate us on some of the critical Cpk's of Intel's process and what sort of sigma's they are seeing on FCCD, DCCD for their poly gate lengths or implant variations, Ion/Ioff ratio, etc...or maybe the binsplit / yield tradeoffs are for pushing higher fmax parts?
Perhaps there are no higher clocked parts on the roadmap, because there is no need to have any at this point. Why would one release something higher than a Conroe 6800 right now or in the near future? What would it be competing against?
It is naive and baseless if you are using current product roadmaps to determine the 65nm process has no headroom. Similarly it is as senseless for the Intel fans to assume OC'ing means more headroom is there, especially if the OC'ing is from voltage increases.
If/when AMD releases a competitor to the 6800, then we will see if there is further headrooom on Intel's 65nm process, however I presume by the time that comes to pass (I'm assuming we won't see any significant K8l/K10 AMD desktop volume until at least Q4) it'll be close enough to 45nm where Intel may not bother pushing the 65nm process that much harder and just focus on the 45nm shrink.
"The truth is that it is nonsense to believe that Penryn will even be released at 4.0Ghz in 2008."
Vroom vroom;)
In other spin news I seem to recall Hector saying that cash position wasn't anything significant.
"We are doing things to improve our cash position, but at this point in time I don't see our balance sheet crying out for any unusual or desperate measures." (Feb 21)
Mar3: http://www.theinquirer.net/default.aspx?article=37982
AMD is seeking to double common stock (additional 750MILLION shares), either to raise money, or prevent an LBO, or both...I guess doubling the common stock is not a an unusual measure! Or perhaps 14 days ago he was not aware of this action and they just stumbled on to this plan in the last week?!?!? I find it amazing that he so blatantly lied (or to be kind, perhaps misled?) folks in that interview such a short time before this action is being taken.
Folks might just want to hold off on buying AMD stock, last I checked doubling the # of shares does not do great things to stock price (unless of course earnings are doubling too!). I'm not an analyst but when one doubles the # of shares, earnings/per share goes...down, P/E ratio goes...up, and higher P/E ratios represents better stock value? (sarcasm).
Of course there may not be any AMD earnings in Q1 or Q2 - a big #/$0 vs a bigger #/$0 will still show up as N/A for P/E....
AMD stockholders prepare to bend over if this passes (gets voted on in May). Of course the other beauty of this arrangement is that unless stockholders specifically vote "no", their vote will be considered approval. I'm not sure what the return rate on these types of measures are, but I'm going to guess it is <50%, so this action will pass by DEFAULT! One would think an action of this type would require a positive vote to approve it. (Of course the reason this is the case is that it would never pass)
Oh and in other, other news, AMD insiders have dumped ~30,000 shares in most recent filings. Always nice for the insiders to dispose of shares before announcing they are going to dilute the hell out of the stock! But what else would you expect from a company of such high moral integrity, right? I hear insider sales is a good sign of management optimism...
Anonymous (seriously people register, it takes nearly 2 seconds, and I know that's not that much time out of your life if you bother posting here) you know you're misreading my comments about performance differences. Yes I could've been more clear, but if you start reading someone's post without making the assumption they're an idiot, you can usually understand them.
Other anonymous, I didn't realize they were doing any architectural tweaks, but a link that actually shows the extent would be nice.
On power usage, I again wasn't careful on how I worded this. I meant to try to say that power usage generated by leakage was not to the extent that the previous anonymous seemed to be arguing it was. In an ideal environment, high k might get the kind of returns he was describing. But those would only be returns in respect to what you described. While Intel will have more control over leakage, my guess is that their current implementation (being that it's an early one) wont really be very revolutionary. I'd assume they'd do a bit more than just a few architectural modifications if that were the case (though if that's exactly what they modified, then a link would, again, be nice).
Yes, I realize I don't work in the industry. I realize there are some things I don't know. I do know that in any industry, there aren't magical process technologies that you can just pull out of your hat and have huge power reductions with.
Also, insiders are dumping share, because they know the stock price will drop due to the increase in shares, and then they can buy more shares at a lower price for when AMD reaps the rewards of Barcelona.
Just because they're doubling the number of shares doesn't mean they're in trouble. Ya, doubling shares doesn't happen all that often, but neither does the sudden usurpation of the largest chip giant from their monopoly either. I'm guessing AMD doesn't need the money to survive, but really wants the money so it can continue to expand aggressively. For proof, you might look at the fact that they are continuing with plans to convert fab 30, build a fab in new york, and continue support with OLPC (which is essentially a charity, and thus doesn't make them a lot of money).
AMD will probably have to rush 45nm, but using immersion lithography doesn't mean they just want to waste money so they have a nicer technology earlier. The same could be said of SOI, IMC, or HT. If these weren't providing some tangible benefit, AMD would've dropped them in no time, because they're a company, and kinda like to make money. Immersion lithography should provide better yields, which AMD obviously wants. It also means they're pre-prepped for its use with 32nm and can make that transition faster.
Greg:
1. There's a name for senior management dumping shares and the buying them back post issuance of new shares with the intent of buying low. It's called "insider trading" and is rewarded with a private room at the Waldorf Astoria - NOT!
2. The decision to commission the NY fab has not been taken. It is due mid 2007 and must be taken at the latest by 2008...after which I suspect AMD loses all the benefits the state of NY has promised them to build the fab.
"Immersion lithography should provide better yields, which AMD obviously wants. It also means they're pre-prepped for its use with 32nm and can make that transition faster."
This is ABSOLUTELY RIDICULOUS. Please explain how immersion "should provide better yields".
Oh and you're they're going to eventually use it anyway argument is pure GENIUS!
Come to think of it I'm gonna need a TV in a few years, I'm still going to use my current one for the next few years, but I might as well buy a new one now as I'll eventually need it! (It's not like the price may come down over time, the performance may improve, or I could invest the money elsewhere until it is needed!). At least I'll be "prepared to use" the new TV.
It's called NPV - buying things early them when it is needed COSTS money!
"1. There's a name for senior management dumping shares and the buying them back post issuance of new shares with the intent of buying low. It's called "insider trading" and is rewarded with a private room at the Waldorf Astoria - NOT!"
Actually, as nefarious as this may seem, the top directors of a company only have a few window of time where they are allowed to buy/sell company stock (to prevent this sort of insider trading). Also I would look at some of these insiders total holdings - while the # of share reported on the INQ/SEC filing are probably fairly small compared to their total holding.
While it LOOKS bad, I doubt it would constitute insider trading.
"Other anonymous, I didn't realize they were doing any architectural tweaks, but a link that actually shows the extent would be nice."
Nice - how about a link backing up "it's just a dumb shrink". Next time when you try to speak authoritatively on a subject, at least do a google search. Wikipedia also has some info, but Wikipedia is not a definitive source as anyone can post anything...
Note it is minor tweaks (as I stated), but it is not a dumb shrink as you claim, and fail to back up with your own link. Additional SSE instructions are the "major" change (and obviously added L2 cache)
"but using immersion lithography doesn't mean they just want to waste money so they have a nicer technology earlier."
Exactly my point. If IBM/AMD could delay using immersion litho they would. Most folks are saying, wow look AMD is using immersion technology earlier than the rest of the industry. I would say the real wow (from a manufacturing perspective) is wow Intel doesn't NEED this new (more expensive, and complicated) technology and is able to extend older technology further.
In fact for the first time in a while, Intel will be able to let others debug new equipment - I think the last time this happened was Cu plating technology (which IBM developed/debugged first)
wow, I didn't realize having an opinion and asking for others to back up their own meant I had to get thrashed. Thanks for keeping this board clean 180.
Taking the wikipedia route (since you guys suggested it).
"Without immersion lithography, the semiconductor industry would have had to pursue the 45 nm node lithography using special techniques such as double patterning on dry lithography tools. Since dry optical resolution is already limited, the ability to control smaller feature sizes is more difficult. Mask costs and yield loss are naturally higher."
So ya, yields are better.
Also, if 45nm is going to be a fast transition (as both companies are showing by their transition plans) then why not use the extra time to develop immersion lithography, just in case 32nm is a slow transition?
Also, to the anonymous I asked for links from. I was not doubting your arguments (though I should have specifically stated this), I was just curious and wanted to know exactly what they were. I do not, however, speak authoritatively on the subject. If I did, I would be saying I had insider information, supplying links, or using less general arguments.
Its nice that not everyone has to be hostile when you express an slightly askew viewpoint because you missed a fact here or there.
Greg - I am trying not to reject any comments unless someone is downright abusive. However, I'll repeat my request to all to try and not make it personal.
Having said that Greg - the more thorough your homework, the better it is for you. This is a blog and there will be folks with differing opinions and they will be poking holes in arguments they don't agree with.
Don't take it to heart...keep on posting.
Wikipedia is NOT a technical information source - it is not peer reviewed by folks with any technical accredition (sp?) whatsoever. However if you could point me to any SCIENTIFIC location (IEEE, IEDM, Sematech, etc), I would be grateful, and apologize.
To say that wikipedia says yield loss is higher using double patterning just means some yahoo posted it as such and noone has yet contradicted it. (It's called the first to make an overt statement game that noone can prove/disprove!).
Had wikipedia said yield is naturally higher with double patterning, it would also be left on there because YIELD INFO IS NOT PUBLIC INFORMATION and it is impossible to refute these types of statements.
And it is also impossible to compare yield between 2 different companies as there are other considerations (transistor lot files/specs will vary and thus so will the process control limits). So the only way to say yield is higher/lower between the two techniques would be for 1 manufacturer to run both processes side by side with all other things being equal.
So ya, it is impossible to say whether yields are better/worse. (unless of course, again, you have some ACTUAL data).
The only data I have seen is Intel's yield curves which they showed when they did a 45nm overview - it shows the same yield trend on 45nm as they have seen on 65nm and 90nm technology nodes. (this of course doesnot mean that double patterning is better or worse, but it does show it is not cratering the yield) Also from technical perspective the fact that the wafer is "immersed" (it's actually a very small amount of fluid in a small area between the wafer and the mask) also introduces all sorts of potential yield/process issues that don't exist on dry patterning. A couple of examples - there are potential residue issues after the field steps, there could be minor variations in film thickness as you try to maintain a uniform film thickness as the wafer steps. Folks who post in wikipedia simply don't have the background on these types of things.
"Also, if 45nm is going to be a fast transition (as both companies are showing by their transition plans) then why not use the extra time to develop immersion lithography, just in case 32nm is a slow transition?"
Not trying to be harsh but this really makes no sense whatsoever. Unless there is a technical need for immersion (which IBM believes) there is no benefit going to it early, just to be "prepared". If the transition to 32nm is slow in your hypothetical case, that means there is more time to develop immersion litho on a 32nm pilot development line and you are spending a lot longer time on more expensive tooling on 45nm. The inverse argument would make more sense - if 32nm was adopted more quickly than expected than it might not allow for adequate time to debug immersion litho tools, thus making use on 45nm more reasonable. However if it is SLOWER that would give more time to take care of it in the normal development phase.
Anonymous, your last point makes sense, and I think I've just had such a negative connotation of CPMs lately that I just blocked out how they actually worked.
I have no idea where you got the idea that I was comparing Intel's dry litho process to AMD's immersion litho process. This just makes absolutely no sense. If you bother reading the argument they make on wikipedia, you'd see they took everything you said into consideration, and then considered the benefits of of IL as well.
Also, I'm not saying wikipedia is a highly credible source, I'm simply taking the advice of a previous poster (though I have no idea who).
180, I'm not saying I shouldn't have to do my research to understand what's being said in here, but I am saying that not having done enough to bring me up to the technical prowess of many of the anonymous posters here shouldn't be reason for ridicule but should in fact be an opportunity to help others get an idea of what's going on in the business.
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