Dailytech got a few seconds with Barcelona - and it does not seem impressive right now:
Quick & Dirty benchmark
An existing Xeon beat the Barcelona even after discounting the clock speed advantage for the Xeon.
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8 comments:
Slow as molASSes.
I think we pretty much seen enough information on how K10 will perform floating points. The result from Cinebench is pretty consistent with POV Ray AMD was showing earlier.
Intel's V8
Another beating AMD is getting at Computex. I'm really starting to think that Intel should focus more on VIA as a bigger threat.
Well, the first two real data ponts for Barcelona have come and gone -- and it is off to a rough start.
Shockingly, too many people are making too much of 'what the clock speed is', this (at this point) is irrelevant, both data points point to the same general statement -- Barcey has not shown tremendous IPC improvement in two rendering apps... this is the key info.
Perhaps it is still buggy and those tweaks to the FPU are not being realized, or perhaps this is what we can expect... nonetheless, I think we are getting an idea why we have not seen engineering preview samples.
Jack come back!
Anonymous said...
Jack come back!
:) no.
"Perhaps it is still buggy and those tweaks to the FPU are not being realized, or perhaps this is what we can expect... nonetheless, I think we are getting an idea why we have not seen engineering preview samples."
The real question will be with the (largely self-imposed) pressure on AMD over K10, will they try to just get it out quickly after fixing some issues (and do further rev's over time) or try to fix the majority of things first (and sacrifice a little bit of the schedule).
Ruiz, et.al have somewhat cornered themselves with "everything's rosy", "no problems here", "manufacturing's on target" comments so I fear AMD will paper launch K10 and then after 2 or 3 additional steppings finally get out the product they want...
I do think people are underestimating what this architecture will be able to do when fully working. Folks are reading a lot into some questionable benchmarks with a chip that is clearly not ready - I don't think this is indicative of K10's architecture. That said unless AMD hits a homerun on their next 1 or 2 steppings (or is sandbagging folks and is deliberately demo'ing poor chips in order to make a big splash later?), it looks like the initial product will be underperforming or paper launched/pushed out.
The problem is Penryn looks like it will keep up with K10 even when it is working properly due to higher clockspeed and if/when Nehalem comes out that may give Intel a susbtantial lead and allow them to start nibbling into AMD's lucrative 4P+ server market share.
Short of fusion (which probably won't matter much in server space and may take a while to gain traction), I don't know what AMD's architecture roadmap is...I would suspect they will have troubling keeping up with Intel's 2 year cycle.
AMD has to be able to outpace Intel in architecture space because I just don't ever seeing them catching Intel on process technology. Intel will be crossed-over on 45nm in Q3'08 (according to Intel), and this is when AMD hopes to start shipping product on a 45nm process which will not at all be comparable from a performance perspective. Despite press reports (and Scientia's HORRENDOUS ANALSYSIS in this area), AMD remains much greater than a year behind Intel in process technology. While they may be ~ 1 year behind PRINTING similar size features, that doesnot mean they are 1 year behind on transistor performance. With AMD's indications of highK& metal gate implementation at end of 45nm node, 32nm node - this puts them art least 2 years behind on gate oxide scaling, which JumpingJack (if he is the real JupmingJack?) can tell you is really the main way they will get transistor speed from 65nm to 45nm (you can play around with strain a bit, implant but much of the blood has been squeezed from that stone)
Anonymous said -
"JumpingJack (if he is the real JupmingJack?) can tell you is really the main way they will get transistor speed from 65nm to 45nm (you can play around with strain a bit, implant but much of the blood has been squeezed from that stone)
"
Yes, this is the real JJ -- formerly home at Tom's, now posting at WWW.XCPUS.COM
No I will not go back. :)
And if you want I could go into my Idsat spiel, but you nailed it pretty much ... also, strain technology dimishes in effectiveness as you go smaller, the reason is strain is induced by stress and stress is a 'pressure' created by two dissimilar materials in contact. In fact, the units for stress are given in MPa (mega pascals) or GPa (giga Pascals) commonly, and a Pascal is a pressure unit. Pressure is force per unit area and strain is a result of the force, so strain directly proportional to Stress*Area, smaller means less strain.
It is completely possible that without something unique, the 45 nm will be like the 65 nm and under perform for max clocks compared to the prior technology (i.e. 65 nm did not show a Fmax scaling improvement compared to 90 nm)...
Jack
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